1. Field of the Invention
The present invention relates to a thin-film semiconductor device, and more particularly to a thin-film semiconductor device having a CMOS structure which is suitable for driving a liquid-crystal display.
2. Description of the Prior Art
Research and development are being actively made in the field of active matrix liquid-crystal displays in which thin-film transistors (TFTs) are made as switching devices for driving every liquid crystal picture element (pixel). Research is also under way on a liquid-crystal display with a built-in driver circuit for driving the above-said TFTs. The built-in driver circuit is constituted by the TFTs directly formed on the liquid-crystal display substrate.
The smallest component in the driver circuit for driving the liquid-crystal display is the inverter which has a CMOS (Complementary Metal Oxide Semiconductor) structure constructed with a pair of n-type and p-type TFTs. Usually, a TFT having a polysilicon semiconductor layer (polysilicon TFT) is used as the above TFT; because polysilicon allows a greater mobility of electrons and holes than amorphous silicon does, and the CMOS structure is easier to construct as the n-type and p-type TFTs can be formed by the same process. The CMOS inverter constructed with polysilicon TFTs having such properties, therefore, offers excellent characteristics in terms of operating frequency and power consumption.
An example of a prior art CMOS inverter is illustrated in FIG. 4. A terminal 33 is the input terminal of the inverter, and a terminal 34 is the output terminal thereof. The lower level potential (low potential) of binary logic is applied to a terminal 31, while the higher level potential (high potential) is applied to a terminal 32.
The terminal 31 to which the low potential is applied is connected to the source of an n-type TFT 35 via contact holes 39. The drain of the n-type TFT 35 is connected to the output terminal 34 of the inverter via contact holes 40. On the other hand, the terminal 32 to which the high potential is applied is connected to the source of a p-type TFT 36 via contact holes 42, and the drain of the p-type TFT 36 is connected to the output terminal 34 of the inverter via contact holes 41. The input terminal 33 of the inverter is connected to the respective gate electrodes 37 and 38 of the TFTs 35 and 36 via contact holes 43.
The potential at the output terminal 34 of the inverter is determined by the potential difference between the terminal 31 and the terminal 32, i.e., the source-drain resistance ratio between the TFTs 35 and 36. That is, when the potential of the input terminal 33 is at a low level, the n-type TFT 35 is OFF, whereas the p-type TFT 36 is ON, which means that the resistance in the p-type TFT 36 is sufficiently low compared with that in the n-type TFT 35. As a result, the high potential applied at the terminal 32 is output at the output terminal 34. Conversely, when the potential of the input terminal 33 is at the high level, the n-type TFT 35 is ON and the p-type TFT 36 is OFF, thus outputting the low potential at the output terminal 34.
Driving the driver circuit of an active matrix liquid-crystal display requires a higher voltage than the voltage (usually 5 Volts) required for driving an ordinary LSI circuit. For example, when using the normally white mode, which is said to be the best display mode currently available in terms of display characteristics, if it is desired to obtain a contrast ratio of 100:1 or higher, a voltage of about 7.5 Volts must be applied to the liquid crystals. Moreover, since the application of a DC voltage over a long period causes degradation in the liquid crystal characteristics, an AC bias must be applied to the liquid crystals.
Therefore, the gate electrode of each TFT (in the liquid crystal panel) for driving the liquid crystals in each pixel must be supplied with a voltage of the magnitude that can retain the stored picture signal for the drain potential of -7.5 Volts when the TFT is OFF; on the other hand, when the TFT is ON, the drain electrode of the TFT must be supplied with a voltage such that a picture signal of 7.5 Volts can be written. Considering the threshold voltage variation, etc. among the TFTs in the liquid crystal panel, it is required that the driver circuit of the active matrix liquid-crystal display be operated with the potential difference, V.sub.hl, of about 20 Volts between the high and low levels.
Generally, as the source-drain voltage of a TFT is increased, a current (leakage current) will appear that flows between the source and drain of the TFT even when a potential to turn off the TFT is applied to the gate electrode thereof.
In FIG. 5, the solid curve shows the drain current I.sub.D as a function of the drain-source voltage V.sub.DS of the n-type TFT 35 when the gate-source voltage V.sub.gs is 0 Volts (putting the n-type TFT 35 in the OFF state).
V.sub.DS corresponds to the voltage that appears at the terminal 34 of the CMOS inverter of FIG. 4 when 0 Volts is applied to the terminal 31. I.sub.D corresponds to the leakage current that flows through the channel region of the n-type TFT 35 when the n-type TFT 35 is in the OFF state.
It can be seen from the characteristic curve shown by the solid curve in FIG. 5 that in the n-type TFT 35 of the prior art inverter, the leakage current (I.sub.D) increases abruptly when V.sub.DS exceeds 15 Volts. This tendency is more apparent in n-type TFTs than in p-type TFTs.
Shown by the solid curve in FIG. 6 is the transfer characteristic of the CMOS inverter of FIG. 4 when V.sub.HL =20 Volts.
When the input voltage V.sub.IN is 0 Volts (the n-type TFT 35 is OFF), the output voltage V.sub.OUT is lower than 20 Volts. This is because, even when V.sub.gs =0 Volts (the n-type TFT 35 is OFF), the resistance in the n-type TFT 35 does not increase sufficiently due to the increased V.sub.DS, as shown in FIG. 4, making the resistance in the p-type TFT 36 appreciable relative to the resistance in the n-type TFT 35. Thus, the effect of voltage drop by the resistance in the p-type TFT appears appreciably in the output voltage V.sub.OUT, causing the output voltage V.sub.OUT to drop below 20 Volts when V.sub.IN =0 Volts.
On the other hand, when V.sub.IN =20 Volts, the output voltage V.sub.OUT is 0 Volts, which is the proper output. This is due to the difference in characteristics between the n-type and p-type TFTs.
Furthermore, the output level of the transfer characteristic is generally low. The inverter having the improper characteristic shown by the solid curve in FIG. 6 has such problems as a slower operating speed, increased susceptibility to malfunction, etc.
The prior art thin-film semiconductor device also has the following problem. Of TFTs in which the channel layer is formed from polysilicon, n-type TFTs generally have greater driving capabilities than p-type TFTs. Therefore, when a CMOS inverter as described above is constructed with polysilicon TFTS, the inverter output inverts at a lower V.sub.IN region since the n-type TFT has a lower resistance.
Such an unbalanced inverter characteristic is shown by the solid curve in FIG. 6. Since the characteristics are not symmetric between the n-type TFT and the p-type TFT, the curve representing the output voltage V.sub.OUT is biased toward the low level side with respect to V.sub.IN. The presence of such a bias in the output voltage V.sub.OUT can lead to a decrease in the inverter operating speed as well as to malfunctioning of the inverter.
The output voltage V.sub.OUT of the inverter is determined by the potential difference V.sub.HL and the resistance ratio between the n-type and p-type TFTs that constitute the inverter. One approach to the correction of the bias in the output voltage V.sub.OUT will be by varying the channel length and width of the respective TFTs, thereby attaining an equal resistance ratio between the TFTs. For example, to attain an equal resistance ratio between the high side (p-type TFT 36) and the low side (n-type TFT 35) in the above inverter, it is required that the p-type TFT 36 has a greater channel width than that of the n-type TFT 35 or that the n-type TFT 35 has a longer channel length than that of the p-type TFT 36.
However, such an approach has the problem in that it involves a decrease in the transfer speed of the inverter and an increase of the inverter area.